nokia Bb5 all ic general info

ARIFGIGANI · 03-14-2009, 08:24 AM

RAP3G

RAP3G is a 3G Radio Application Processor
Successor for TIKU (used in NOKIA 7600) with some technical improvements and additional features
In general RAP3G consists of three separate parts:
Processor subsystem (PSS) that includes ARM926 MCU as a main processor, Lead3 PH3 DSP and related functions
MCU peripherals
DSP peripherals
RAP3G is running with NOS and takes care of all cellular modem activities
RAP3G core voltage (1.40V) is generated from TAHVO VCORE and I/O voltage (1.8V) is from RETU VIO. Core voltage in sleep mode is lowered to 1.05V

RETU

RETU is the primary EM ASIC including following functional blocks:
Start up logic and reset control
Charger detection
Battery voltage monitoring
32.768kHz clock with external crystal
Real time clock with external backup battery
SIM card interface
Stereo audio codecs and amplifiers
A/D converter
Regulators
Vibra interface
Digital interface (CBUS)
RETU ASIC does not include security functions such as UEM(E,K)

TAHVO

TAHVO is the secondary EM ASIC including following functional blocks:
Core supply generation (VCORE & VCOREA)
Charge control circuitry
Level shifter and regulator for USB/FBUS
Current gauge for battery current measuring
External LED driver control interface
Digital interface (CBUS)
TAHVO ASIC does not include security functions such as UEM(E,K)

CMT Flash
CMT Flash memory is used to store:
MCU program code
DSP program code
Tuning values
Certificates
Capacity: 64Mbit
Logic and supply voltage for NOR Flash is supplied from VIO (1.8V)
Flash clock is 48MHz (192MHz/4)

CMT SDRAM

CMT SDRAM is mainly used as a dynamic data storage for MCU data
Capacity: 64MBit
SDRAM core voltage (1.8V) is generated by RETU’s VDRAM regulator
I/O voltage (1.8V) is generated by RETU’s VIO regulator
SDRAM clock is 96MHz (192MHz/2)

OMAP 1710

OMAP is the application processor running with Symbian operating system (EPOC)
Platform for executing all user related application. Main interfaces:
Camera interface
Display interface
Bluetooth interface
MMC interface
USB interface
Keyboard interface
X-Bus for communication with RAP3G
OMAP is a standard ASIC designed by Texas Instruments and used also by other manufacturers of mobile phones and handheld PCs
Core voltage VCORE=1.4V is generated by discrete SMPS, and is lowered to 1.09V in sleep mode
I/O voltage VIO=1.8V is generated by RETU

APE Combo Memory
APE Flash is used to store application code and user data
It is not possible to execute code directly from Flash -> executables need first to be loaded to DDR and run from there
Capacity: 256Mbit (Flash), 256Mbit (DDR)
Core voltage for DDR is VDRAM 1.8V
VIO 1.8V is for DDR I/O voltage
Both NAND core and I/O voltages are generated by RETU
DDR clock is 110MHz (220MHz/2)
Flash interface speed is 22MHz

Product Specific Circuitries

Front Camera
The front camera is controlled and its data is collected by OMAP
The I/O voltage of OMAP is 1.8V, and the one of the camera is 2.8V; therefore a level shifter is needed
The camera is powered with two different voltages from LDO (Low-dropout voltage) regulators:
VCAM 1.5V for camera digital circuits, and sensor A/D-converter
VCAM2 2.8V for camera I/O, and sensor photo diode
[Only registered and activated users can see links. ]

03-14-2009, 08:24 AM	#1 (permalink)
ARIFGIGANI Junior Member Join Date: Dec 2008 Posts: 17 Thanks: 16 Thanked 20 Times in 8 Posts Rep Power: 0	nokia Bb5 all ic general info RAP3G RAP3G is a 3G Radio Application Processor Successor for TIKU (used in NOKIA 7600) with some technical improvements and additional features In general RAP3G consists of three separate parts: Processor subsystem (PSS) that includes ARM926 MCU as a main processor, Lead3 PH3 DSP and related functions MCU peripherals DSP peripherals RAP3G is running with NOS and takes care of all cellular modem activities RAP3G core voltage (1.40V) is generated from TAHVO VCORE and I/O voltage (1.8V) is from RETU VIO. Core voltage in sleep mode is lowered to 1.05V RETU RETU is the primary EM ASIC including following functional blocks: Start up logic and reset control Charger detection Battery voltage monitoring 32.768kHz clock with external crystal Real time clock with external backup battery SIM card interface Stereo audio codecs and amplifiers A/D converter Regulators Vibra interface Digital interface (CBUS) RETU ASIC does not include security functions such as UEM(E,K) TAHVO TAHVO is the secondary EM ASIC including following functional blocks: Core supply generation (VCORE & VCOREA) Charge control circuitry Level shifter and regulator for USB/FBUS Current gauge for battery current measuring External LED driver control interface Digital interface (CBUS) TAHVO ASIC does not include security functions such as UEM(E,K) CMT Flash CMT Flash memory is used to store: MCU program code DSP program code Tuning values Certificates Capacity: 64Mbit Logic and supply voltage for NOR Flash is supplied from VIO (1.8V) Flash clock is 48MHz (192MHz/4) CMT SDRAM CMT SDRAM is mainly used as a dynamic data storage for MCU data Capacity: 64MBit SDRAM core voltage (1.8V) is generated by RETU’s VDRAM regulator I/O voltage (1.8V) is generated by RETU’s VIO regulator SDRAM clock is 96MHz (192MHz/2) OMAP 1710 OMAP is the application processor running with Symbian operating system (EPOC) Platform for executing all user related application. Main interfaces: Camera interface Display interface Bluetooth interface MMC interface USB interface Keyboard interface X-Bus for communication with RAP3G OMAP is a standard ASIC designed by Texas Instruments and used also by other manufacturers of mobile phones and handheld PCs Core voltage VCORE=1.4V is generated by discrete SMPS, and is lowered to 1.09V in sleep mode I/O voltage VIO=1.8V is generated by RETU APE Combo Memory APE Flash is used to store application code and user data It is not possible to execute code directly from Flash -> executables need first to be loaded to DDR and run from there Capacity: 256Mbit (Flash), 256Mbit (DDR) Core voltage for DDR is VDRAM 1.8V VIO 1.8V is for DDR I/O voltage Both NAND core and I/O voltages are generated by RETU DDR clock is 110MHz (220MHz/2) Flash interface speed is 22MHz Product Specific Circuitries Front Camera The front camera is controlled and its data is collected by OMAP The I/O voltage of OMAP is 1.8V, and the one of the camera is 2.8V; therefore a level shifter is needed The camera is powered with two different voltages from LDO (Low-dropout voltage) regulators: VCAM 1.5V for camera digital circuits, and sensor A/D-converter VCAM2 2.8V for camera I/O, and sensor photo diode [Only registered and activated users can see links. ]

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